Prior to explaining the present invention, a constitution of a conventional general PLL will be described.
As shown in FIG. 24(A), a conventional PLL comprises a phase comparator 101, a charge pump 102, a low pass filter (LPF) 103, a voltage controlled oscillator (VCO) 104, and a frequency divider 105.
As shown in FIGS. 24(A) and (B), the phase comparator 101 compares an input waveform with a divided waveform obtained by dividing an output waveform of the VCO 104 by the frequency divider 105. Further, it performs an operation to detect how much a phase of the divided waveform is delayed from a phase of the input waveform, and an operation to detect how much the phase of the divided waveform is ahead of the phase of the input waveform. It is to be noted that FIG. 24(B) shows a detected lag component of the phase in the form of a waveform b-1 and a detected lead component of the phase in the form of a waveform b-2. Here, a phase difference is represented with a pulse width.
Then, the charge pump 102 combines the lag component (b-1) and the lead component (b-2) into one signal (c) and amplifies the thus combined signal. Here, a polarity of a pulse of the lead component is inverted.
Subsequently, the LPF 103 eliminates a high-frequency component in the combined waveform (c), and converts a pulse width representing the phase difference into a voltage (d). Here, as shown in FIG. 25(A), a voltage is high as the phase difference of the lag component is large, and the voltage is low as the phase difference of the lead component is large.
The VCO 104 converts the voltage into a delay time (free running frequency of the oscillator). As shown in FIG. 25(B), an oscillatory frequency becomes high and the phase advances as an output voltage (VCO voltage) of the LPF 104 is high, and the oscillatory frequency becomes low and the phase is delayed as the output voltage is low.
Furthermore, the frequency divider 105 divides an output waveform of the VCO, and generates a divided waveform obtained by converting the obtained result into a frequency in the vicinity of a frequency of the input waveform.
As described above, in the PLL, the output waveform is feedback-controlled in such a manner that the phase of the divided waveform and the phase of the input waveform become fixed.
A structure of a conventional general DLL will now be described.
As shown in FIG. 26(A), a DLL according to a prior art comprises a phase comparator 101, a charge pump 102, a low pass filter (LPF) 103, and a variable delay circuit 106.
As shown in FIG. 26(B), the phase comparator 101, the charge pump 102 and the LPF 104 detect a lead, a lag and their degrees (b-1, b-2) of a phase of an output waveform to a phase of an input waveform like the example of the PLL mentioned above, convert a phase difference (c) into a voltage difference (d), and input the result to the variable delay circuit (DELAY) 106. Here, as shown in FIG. 27(A), likewise, the voltage is high as the phase difference of a lag component is large, and the voltage is low as the phase difference of a lead component is large.
Moreover, the DELAY 106 converts the voltage difference into a delay time like the VCO 105. As shown in FIG. 27(B), a propagation delay time of the output waveform to the input waveform is short as an output voltage (DELAY voltage) of the LPF 104 is high, and the propagation delay time is long as the output voltage is low.
As described above, in the DLL, the delay time is feedback-controlled in such a manner that the phases of the output waveform and the input waveform become fixed.
Meanwhile, in FIG. 25(A) and FIG. 27(A), a relationship between the phase difference and the VCO voltage is shown in the form of linear graphs, but it is not necessarily linear in a practical sense. When an SR latch is utilized for the phase comparator in particular, the linearity of the VCO voltage (or the DELAY voltage) is especially poor in the vicinity of a point where the phase difference is zero as shown in FIG. 28. Therefore, in the conventional PLL or DLL, there is a problem that the accuracy of the phase lock is deteriorated. For example, since a pulse width which passes through a CMOS logic gate is finite, it is determined that there is “no phase difference” in some cases even if a phase difference is actually produced.
Additionally, the above-described PLL or DLL according to the prior art comprises an analog circuit. Therefore, there are problems that a power consumption is large, a circuit scale is increased and a cost is high.
For example, a circuit in which an OP amplifier is used for the phase comparator has large power consumption and is hard to be reduced in size. Further, a circuit in which PMOS and NMOS analog switches and an OP amplifier are used for the charge pump also has large power consumption and is hard to be reduced in size.
Furthermore, in regard to a regulator which changes a voltage variable range of the VCO or the DELAY, a power consumption becomes large when an operating speed is increased, and a dimension of the regulator also becomes large. Therefore, this can be an obstacle in increasing a lock loop frequency band.
Moreover, since the analog circuit includes a circuit whose response speed is low such as an OP amplifier or an LPF, it is hard to perform phase locking with the high accuracy in a high frequency band in the PLL or DLL using the conventional analog circuit.
Additionally, in recent years, as a frequency of an operating clock of a semiconductor integrated circuit becomes high, there is a demand of high timing accuracy without a skew. However, in a large-scale chip such as a logic circuit, there is a problem that a skew is generated between parts distanced from each other on the chip due to irregularities in characteristics of relay buffers for clock signals.
It is to be noted that an example of the digital-controlled DLL is disclosed in Japanese Patent Application Laid-open No. 2000-124779. According to the technique disclosed in this publication, until the phase locking is applied, a lead or a lag of a phase is detected, a detection result is represented by using a binary counter, setting of a delay circuit is performed by binary search combined with a decoder, and a count value is increased or decreased one by one after the locking is applied. As a result, a lockup time is reduced, and the accuracy of an output frequency is improved.
However, in a binary search operation in which the binary counter is combined with the decoder, values of a plurality of bits may be simultaneously reversed in some cases. Therefore, a so-called whisker may be applied to a selector of the delay circuit, which may possibly lead to a malfunction. For example, when a value of the binary counter is counted up from “01111” to “10000”, all the bits are reversed. As a result, a plurality of delay circuits are simultaneously selected by a skew of the decoder, and a whisker may possibly occurs in a clock.
In view of the above-described problems, it is an object of the present invention to provide digitally-controlled PLL and DLL which have small power consumption, can be readily reduced in size, enable a locked loop in a high frequency band and have the high reliability, a timing generator utilizing the DLL, a semiconductor test instrument including the timing generator, and a semiconductor integrated circuit including the PLL.